24 May 2013 
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If you would like to respond to a currently open ITT you will have to register first as a 'New User' with the EMITS (Electronic Mail Invitation to Tender) system.

"Always Open" Calls for Proposals have been issued for the following:
*ARTES 3-4 - This is listed in EMITS under number AO/1-5891
*ARTES 5.2 - This is listed in EMITS under number AO/1-6000.
*Newcomers' Initiative - This is listed in EMITS under number AO/1-5658

For a list of ARTES 20 IAP tenders please see the IAP website.

Low-cost MMIC Chipset for future broadband VSAT (*)
Programme Element: ARTES 5.1
Reference nr.: 13.1TT.47
Planned Tender Issue: quarter 4, 2013

(*) Priority 2
Objective: To design, manufacture and test a complete MMIC chipset, based on European technology, for future broadband Ka-band VSAT.
Targeted Improvements: Our goal is to limit industry dependence on US suppliers. Fivefold increase of the bandwidth: operation over the full extended Ka-band offering a total bandwidth of 2.5 GHz against the 500 MHz of today.
Description:
The next generation Ka-band satellite systems target system capacities ten times higher than the current systems. To achieve this goal it will be necessary to use the full extended Ka-band that offers a total bandwidth of 2.5 GHz as compared to the today's 500 MHz (19.7 - 20.2 GHz downlink; 29.5 - 30 GHz uplink).
The main technology challenge for the user terminal will be the development of LNB (Low Noise Block) and BUC (Block Up-Converter) able to operate over the full extended Ka-band, thus offering a 2.5 GHz coverage while still interfacing with a standard L-band modem operating from 950 MHz up to 1450 MHz. This implies the availability of specific low-cost monolithic microwave integrated circuits (MMICs).
The objective of activity is to design, manufacture and test a complete chipset that will cover low noise amplification (17.3 up to 20.2 GHz ) and down-conversion to L-band, up-conversion from L-band and power amplification (27.5 up to 30 GHz). The packaged MMICs shall be based on European technology.
Work logic:
- Architectural trade-off and functional blocks definition.
- First iteration of chipset design, manufacture and test.
- Second iteration of chipset design, manufacture and test.

(*) Priority 2 activities will only be initiated on the explicit request of at least one delegation.
 

Last Update: 27 Nov 2012
 
 
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